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Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density.

, , and . FPGA, page 37-46. ACM, (1999)

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Timing-driven placement for FPGAs., , and . FPGA, page 203-213. ACM, (2000)Automatic generation of FPGA routing architectures from high-level descriptions., and . FPGA, page 175-184. ACM, (2000)Are FPGAs suffering from the innovator's dilemna?, and . FPGA, page 135-136. ACM, (2013)FPGA challenges and opportunities at 40nm and beyond.. FPL, page 4. IEEE, (2009)Tatum: Parallel Timing Analysis for Faster Design Cycles and Improved Optimization., and . FPT, page 110-117. IEEE, (2018)Feel Free to Interrupt: Safe Task Stopping to Enable FPGA Checkpointing and Context Switching., and . ACM Trans. Reconfigurable Technol. Syst., 13 (1): 3:1-3:27 (2020)Automatic Application-Specific Calibration to Enable Dynamic Voltage Scaling in FPGAs., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (12): 3095-3108 (2018)Slack Allocation and Routing to Improve FPGA Timing While Repairing Short-Path Violations., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (4): 686-697 (2008)You Cannot Improve What You Do not Measure: FPGA vs. ASIC Efficiency Gaps for Convolutional Neural Network Inference., , and . ACM Trans. Reconfigurable Technol. Syst., 11 (3): 20:1-20:23 (2018)Wotan: Evaluating FPGA Architecture Routability without Benchmarks., and . ACM Trans. Reconfigurable Technol. Syst., 11 (2): 11:1-11:23 (2018)