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Scaling CMOS beyond Si FinFET: an analog/RF perspective.

B. Parvais, G. Hellings, M. Simicic, P. Weckx, J. Mitard, D. Jang, V. Deshpande, B. van Liempc, A. Veloso, A. Vandooren, N. Waldron, P. Wambacq, N. Collaert, and D. Verkest. ESSDERC, page 158-161. IEEE, (2018)

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Jérôme Huppertz

Modulation inflammatorischer Prozesse mittels GPI-verankerter Chemokin-AnalogaJ. Huppertz. Uni München, (2009)

Jérôme Clerc

Jérôme Boucher

Jérôme Krets

Jérôme Feret

Other publications of authors with the same name

CDM-Time Domain Turn-on Transient of ESD Diodes in Bulk FinFET and GAA NW Technologies.S. Chen, D. Linten, G. Hellings, M. Simicic, B. Kaczer, T. Chiarella, H. Mertens, J. Mitard, A. Mocuta, and N. Horiguchi. IRPS, page 1-7. IEEE, (2019)Low-power DRAM-compatible Replacement Gate High-k/Metal Gate stacks.R. Ritzenthaler, T. Schram, E. Bury, J. Mitard, L. Ragnarsson, G. Groeseneken, N. Horiguchi, A. Thean, A. Spessot, C. Caillat and 2 other author(s). ESSDERC, page 242-245. IEEE, (2012)Detecting Transistor Defects in Medical Systems Using a Multi Model Ensemble of Convolutional Neural Networks.H. Koçak, A. Naskali, Ö. Pinarer, and J. Mitard. IEEE BigData, page 4731-4737. IEEE, (2021)Scaling CMOS beyond Si FinFET: an analog/RF perspective.B. Parvais, G. Hellings, M. Simicic, P. Weckx, J. Mitard, D. Jang, V. Deshpande, B. van Liempc, A. Veloso, A. Vandooren and 4 other author(s). ESSDERC, page 158-161. IEEE, (2018)Experimental analysis of buried SiGe pMOSFETs from the perspective of aggressive voltage scaling.F. Crupi, M. Alioto, J. Franco, P. Magnone, B. Kaczer, G. Groeseneken, J. Mitard, L. Witters, and T. Hoffmann. ISCAS, page 2249-2252. IEEE, (2011)Superior reliability and reduced Time-Dependent variability in high-mobility SiGe channel pMOSFETs for VLSI logic applications.J. Franco, B. Kaczer, J. Mitard, M. Toledano-Luque, F. Crupi, G. Eneman, P. Rousse, T. Grasser, M. Cho, T. Kauerauf and 6 other author(s). ICICDT, page 1-4. IEEE, (2012)Scalability comparison between raised- and embedded-SiGe source/drain structures for Si0.55Ge0.45 implant free quantum well pFET.S. Yamaguchi, L. Witters, J. Mitard, G. Eneman, G. Hellings, A. Hikavyy, R. Loo, and N. Horiguchi. Microelectron. Reliab., (2018)Towards high performance sub-10nm finW bulk FinFET technology.T. Chiarella, S. Kubicek, E. Rosseel, R. Ritzenthaler, A. Hikavyy, P. Eyben, A. Keersgieter, L. Ragnarsson, M. Kim, S. Chew and 10 other author(s). ESSDERC, page 131-134. IEEE, (2016)Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning.H. Mertens, M. Hosseini, T. Chiarella, D. Zhou, S. Wang, G. Mannaert, E. Dupuy, D. Radisic, Z. Tao, Y. Oniki and 30 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)Molybdenum Nitride as a Scalable and Thermally Stable pWFM for CFET.H. Arimura, S. Brus, J. Franco, Y. Oniki, A. Vandooren, T. Conard, B. Chan, B. Kannan, M. Samiee, W. Li and 11 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)

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Disambiguation of "Mitard, Jérôme"

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Scaling CMOS beyond Si FinFET: an analog/RF perspective.

Please choose a person to relate this publication to

Jérôme Huppertz

Jérôme Clerc

Jérôme Boucher

Jérôme Krets

Jérôme Feret

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Mitard, Jérôme"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Scaling CMOS beyond Si FinFET: an analog/RF perspective.

Please choose a person to relate this publication to

Jérôme Huppertz

Jérôme Clerc

Jérôme Boucher

Jérôme Krets

Jérôme Feret

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Scaling CMOS beyond Si FinFET: an analog/RF perspective.