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Disambiguation of "Badaroglu, Mustafa"

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TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes.

, , , , , , , , , , , and . DAC, page 24:1-24:6. ACM, (2013)

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Mustafa Mustafa

Mustafa Zaki Mustafa

Mustafa Kabisch

Mustafa Çagatay

Arafa Mustafa

 

Other publications of authors with the same name

Modeling of Substrate Noise Generation, Isolation, and Impact for an LC-VCO and a Digital Modem on a Lightly-Doped Substrate., , , , , , and . IEEE J. Solid State Circuits, 41 (9): 2040-2051 (2006)Scalable Gate-Level Models for Power and Timing Analysis., , , , , and . ISCAS, page 2938-2941. IEEE, (2007)System-Level Simulation of Electromigration in a 3 nm CMOS Power Delivery Network: The Effect of Grid Redundancy, Metallization Stack and Standard-Cell Currents., , , , and . IRPS, page 1-7. IEEE, (2022)BANDIT: embedding analog-to-digital converters on digital telecom ASICs., , , , , , , , , and 1 other author(s). ICECS, page 1377-1380. IEEE, (1999)Modeling and experimental verification of substrate noise generation in a 220-Kgates WLAN system-on-chip with multiple supplies., , , , , , , and . IEEE J. Solid State Circuits, 38 (7): 1250-1260 (2003)SWAN: high-level simulation methodology for digital substrate noise generation., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 14 (1): 23-33 (2006)High-level simulation of substrate noise generation from large digital circuits with multiple supplies., , , , , , , and . DATE, page 326-330. IEEE Computer Society, (2001)Interconnect-Aware Technology and Design Co-Optimization for the 5-nm Technology and Beyond.. J. Low Power Electron., 14 (2): 186-194 (2018)Evolution of substrate noise generation mechanisms with CMOS technology scaling., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 53-I (2): 296-305 (2006)Analog-Digital Partitioning for Low-Power UWB Impulse Radios under CMOS Scaling., , , , , , and . EURASIP J. Wireless Comm. and Networking, (2006)