( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase-Frequency Detection.

, , , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 62-II (9): 836-840 (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Chu Duc

Xiaolan Chu

Chengcai Chu

Pakong Chu

Chengbin Chu

 

Другие публикации лиц с тем же именем

A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- Gm Bias., , , , , , , , и . IEEE J. Solid State Circuits, 51 (10): 2312-2327 (2016)A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65nm CMOS process., , , , , и . A-SSCC, стр. 101-104. IEEE, (2014)A Crystal-Less Programmable Clock Generator with RC-LC Hybrid Oscillator for GHz Applications in 14 nm FinFET CMOS., , , , , и . BCICTS, стр. 263-266. IEEE, (2018)A Four-Channel 32-Gb/s Transceiver With Current-Recycling Output Driver and On-Chip AC Coupling in 65-nm CMOS Process., , , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (5): 304-308 (2014)A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel., , , , , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (12): 1432-1436 (2017)An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase-Frequency Detection., , , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 62-II (9): 836-840 (2015)A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process., , , , , , , и . IEEE J. Solid State Circuits, 50 (11): 2603-2612 (2015)A Programmable On-Chip Reference Oscillator With Slow-Wave Coplanar Waveguide in 14-nm FinFET CMOS., , , , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 67-II (10): 1834-1838 (2020)An all-digital bang-bang PLL using two-point modulation and background gain calibration for spread spectrum clock generation., , , , , и . VLSIC, стр. 136-. IEEE, (2015)6.4 A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier., , , , , , , , , и 9 other автор(ы). ISSCC, стр. 122-124. IEEE, (2020)