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Disambiguation of "Chu, Sang-Hyeok"

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A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65nm CMOS process.

, , , , , and . A-SSCC, page 101-104. IEEE, (2014)

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Chu Duc

Xiaolan Chu

Chengcai Chu

Pakong Chu

Yingyi Chu

 

Other publications of authors with the same name

A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65nm CMOS process., , , , , and . A-SSCC, page 101-104. IEEE, (2014)A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- Gm Bias., , , , , , , , and . IEEE J. Solid State Circuits, 51 (10): 2312-2327 (2016)A Crystal-Less Programmable Clock Generator with RC-LC Hybrid Oscillator for GHz Applications in 14 nm FinFET CMOS., , , , , and . BCICTS, page 263-266. IEEE, (2018)A Four-Channel 32-Gb/s Transceiver With Current-Recycling Output Driver and On-Chip AC Coupling in 65-nm CMOS Process., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (5): 304-308 (2014)An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase-Frequency Detection., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 62-II (9): 836-840 (2015)A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel., , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (12): 1432-1436 (2017)A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process., , , , , , , and . IEEE J. Solid State Circuits, 50 (11): 2603-2612 (2015)An all-digital bang-bang PLL using two-point modulation and background gain calibration for spread spectrum clock generation., , , , , and . VLSIC, page 136-. IEEE, (2015)A Programmable On-Chip Reference Oscillator With Slow-Wave Coplanar Waveguide in 14-nm FinFET CMOS., , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 67-II (10): 1834-1838 (2020)A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm., , , , , , , , and . A-SSCC, page 1-4. IEEE, (2015)