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Disambiguation of "Zeydel, Bart R."

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Energy-Efficient Design Methodologies: High-Performance VLSI Adders.

, , and . IEEE J. Solid State Circuits, 45 (6): 1220-1233 (2010)

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Bart Cramer

Bart Maris

Bart Kersbergen

Bart Riel

Bart Geurts

 

Other publications of authors with the same name

Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders., , , , and . IEEE Symposium on Computer Arithmetic, page 272-279. IEEE Computer Society, (2003)Methodology for Energy-Efficient Digital Circuit Sizing: Important Issues and Design Limitations., and . PATMOS, volume 4148 of Lecture Notes in Computer Science, page 127-136. Springer, (2006)Energy-Efficient Design Methodologies: High-Performance VLSI Adders., , and . IEEE J. Solid State Circuits, 45 (6): 1220-1233 (2010)Energy Optimization of High-Performance Circuits., , and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 399-408. Springer, (2003)Logic Style Comparison for Ultra Low Power Operation in 65nm Technology., , , and . PATMOS, volume 4644 of Lecture Notes in Computer Science, page 181-190. Springer, (2007)Energy minimization method for optimal energy-delay extraction., , and . ESSCIRC, page 177-180. IEEE, (2003)Efficient Mapping of Addition Recurrence Algorithms in CMOS., , and . IEEE Symposium on Computer Arithmetic, page 107-113. IEEE Computer Society, (2005)Circuit Design Style for Energy Efficiency: LSDL and Compound Domino., , , , and . PATMOS, volume 4148 of Lecture Notes in Computer Science, page 47-55. Springer, (2006)Circuit Sizing and Supply-Voltage Selection for Low-Power Digital Circuit Design., , and . PATMOS, volume 4148 of Lecture Notes in Computer Science, page 148-156. Springer, (2006)Low- and Ultra Low-Power Arithmetic Units: Design and Comparison., , and . ICCD, page 249-252. IEEE Computer Society, (2005)