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Reducing the Hamming distance of encoded FFT twiddle factors using improved heuristic algorithms., , и . LASCAS, стр. 1-4. IEEE, (2013)The Radix-2m Squared Multiplier., , , , и . ICECS, стр. 1-4. IEEE, (2020)Exploring Approximate Arithmetic Units for a Power-Efficient Kalman Gain VLSI Design., , , , и . ICECS 2022, стр. 1-4. IEEE, (2022)Design of a radix-2m hybrid array multiplier using carry save adder format., , , и . SBCCI, стр. 172-177. ACM, (2005)Minimum number of operations under a general number representation for digital filter synthesis., , , и . ECCTD, стр. 252-255. IEEE, (2007)Enhancing a HEVC interpolation filter hardware architecture with efficient adder compressors., , , и . NEWCAS, стр. 1-4. IEEE, (2015)Low power SATD architecture employing multiple sizes Hadamard Transforms and adder compressors., , , , и . NEWCAS, стр. 277-280. IEEE, (2017)Optimization of Single-Stage FFT Architectures Using Multiple Constant Multiplication., , , и . SBCCI, стр. 1-6. IEEE, (2018)A New Architecture for Signed Radix-2m Pure Array Multipliers., , и . ICCD, стр. 112-117. IEEE Computer Society, (2002)Energy-efficient Gaussian filter for image processing using approximate adder circuits., , , и . ICECS, стр. 450-453. IEEE, (2015)