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Power-efficient sum of absolute differences architecture using adder compressors., , , и . ICECS, стр. 340-343. IEEE, (2016)Low power sum of absolute differences architecture using novel hybrid adder., , , , и . LASCAS, стр. 1-4. IEEE, (2017)Power-Efficient Sum of Absolute Differences Hardware Architecture Using Adder Compressors for Integer Motion Estimation Design., , , , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (12): 3126-3137 (2017)A power-efficient 4-2 Adder Compressor topology., , , , , и . NEWCAS, стр. 281-284. IEEE, (2017)Multi-Size Inverse DCT-II Hardware Design for the VVC Decoder., , , , и . LASCAS, стр. 1-4. IEEE, (2023)Multiple Transform Selection Hardware Design for 4K@60fps Real-Time Versatile Video Coding., , , , и . ISCAS, стр. 1-5. IEEE, (2022)SATD hardware architecture based on 8×8 Hadamard Transform for HEVC encoder., , , и . ICECS, стр. 576-579. IEEE, (2015)Exploiting absolute arithmetic for power-efficient sum of absolute differences., , , , , , и . ICECS, стр. 522-525. IEEE, (2017)Exploring the use of parallel prefix adder topologies into approximate adder circuits., , , , и . ICECS, стр. 298-301. IEEE, (2017)A Hardware Design for the Multi-Transform Module of the Versatile Video Coding Standard., , , и . SBCCI, стр. 1-6. IEEE, (2023)