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Disambiguation of "U., Seng-Pan"

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A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation.

, , , , , and . IEEE J. Solid State Circuits, 47 (11): 2614-2626 (2012)

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Peter Seng

Stefan Seng

Katja Seng

Helmut Seng

Gerhard Seng

 

Other publications of authors with the same name

A novel low-voltage finite-gain compensation technique for high-speed reset- and switched-opamp circuits., , and . ISCAS, IEEE, (2006)On the Design of a Programmable-Gain Amplifier With Built-In Compact DC-Offset Cancellers for Very Low-Voltage WLAN Systems., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (2): 496-509 (2008)A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations., , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (1): 354-363 (2017)A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation., , , , , and . IEEE J. Solid State Circuits, 47 (11): 2614-2626 (2012)A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (3): 572-583 (2018)Generalized Circuit Techniques for Low-Voltage High-Speed Reset- and Switched-Opamps., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (8): 2188-2201 (2008)Metastablility in SAR ADCs., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (2): 111-115 (2017)A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Δ Σ Modulator With Multirate Opamp Sharing., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (10): 2641-2654 (2017)A frequency up-conversion and two-step channel selection embedded CMOS D/A interface., , , , and . ISCAS (1), page 392-395. IEEE, (2005)An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H., , , , , , , , and . ESSCIRC, page 218-221. IEEE, (2010)