( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Parity check for m-of-n delay insensitive codes.

, , и . IOLTS, стр. 157-162. IEEE, (2013)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Josef Ney

Robert Ney

Michael Ney

Verena Ney

Hans Ney

 

Другие публикации лиц с тем же именем

Router architecture for high-performance NoCs., , и . SBCCI, стр. 111-116. ACM, (2007)Triple Rail Logic Robustness against DPA., , , , , , и . ReConFig, стр. 415-420. IEEE Computer Society, (2008)A monitored NoC with runtime path adaptation., , , , и . ISCAS, стр. 1965-1968. IEEE, (2014)QoS in Networks-on-Chip - Beyond Priority and Circuit Switching Techniques., , и . VLSI-SoC (Selected Papers), том 291 из IFIP, стр. 1-22. Springer, (2007)PaDReH: a framework for the design and implementation of dynamically and partially reconfigurable systems., , , и . SBCCI, стр. 10-15. ACM, (2004)H2A: A hardened asynchronous network on chip., , и . SBCCI, стр. 1-6. IEEE, (2013)Parity check for m-of-n delay insensitive codes., , и . IOLTS, стр. 157-162. IEEE, (2013)SPP-NIDS - A Sea of Processors Platform for Network Intrusion Detection Systems., , , , и . IEEE International Workshop on Rapid System Prototyping, стр. 27-33. IEEE Computer Society, (2007)Lasio 3D NoC vertical links serialization: Evaluation of latency and buffer occupancy., , , , , и . SBCCI, стр. 1-6. IEEE, (2013)Evaluation of current QoS Mechanisms in Networks on Chip., , , и . SoC, стр. 1-4. IEEE, (2006)