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Disambiguation of "Pontes, Julian J. H."

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Parity check for m-of-n delay insensitive codes.

, , and . IOLTS, page 157-162. IEEE, (2013)

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Julian H Sprau

Julian J Zemke

H J Plüss

H -J Bielig

J. H. Merkin

 

Other publications of authors with the same name

IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management., , , , , , , , , and 18 other author(s). IEEE J. Solid State Circuits, 56 (1): 79-97 (2021)Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event Effects., , and . ASYNC, page 142-149. IEEE Computer Society, (2012)H2A: A hardened asynchronous network on chip., , and . SBCCI, page 1-6. IEEE, (2013)Parity check for m-of-n delay insensitive codes., , and . IOLTS, page 157-162. IEEE, (2013)Two-phase protocol converters for 3D asynchronous 1-of-n data links., , and . ASP-DAC, page 154-159. IEEE, (2015)An accurate Single Event Effect digital design flow for reliable system level design., , and . DATE, page 224-229. IEEE, (2012)Hermes-AA: A 65nm asynchronous NoC router with adaptive routing., , , and . SoCC, page 493-498. IEEE, (2010)Soft error mitigation in asynchronous networks on chip.. Pontifícia Universidade Católica do Rio Grande do Sul, Porto Alegre, Brazil, (2012)ndltd.org (oai:tede2.pucrs.br:tede/5198).Hermes-A - An Asynchronous NoC Router with Distributed Routing., , , and . PATMOS, volume 6448 of Lecture Notes in Computer Science, page 150-159. Springer, (2010)Tradeoffs between RTO and RTZ in WCHB QDI asynchronous design., , and . ISQED, page 692-699. IEEE, (2014)