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PaDReH: a framework for the design and implementation of dynamically and partially reconfigurable systems., , , and . SBCCI, page 10-15. ACM, (2004)A monitored NoC with runtime path adaptation., , , , and . ISCAS, page 1965-1968. IEEE, (2014)H2A: A hardened asynchronous network on chip., , and . SBCCI, page 1-6. IEEE, (2013)Router architecture for high-performance NoCs., , and . SBCCI, page 111-116. ACM, (2007)Parity check for m-of-n delay insensitive codes., , and . IOLTS, page 157-162. IEEE, (2013)Triple Rail Logic Robustness against DPA., , , , , , and . ReConFig, page 415-420. IEEE Computer Society, (2008)QoS in Networks-on-Chip - Beyond Priority and Circuit Switching Techniques., , and . VLSI-SoC (Selected Papers), volume 291 of IFIP, page 1-22. Springer, (2007)Evaluation of current QoS Mechanisms in Networks on Chip., , , and . SoC, page 1-4. IEEE, (2006)Evaluation on FPGA of triple rail logic robustness against DPA and DEMA., , , , , and . DATE, page 634-639. IEEE, (2009)Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event Effects., , and . ASYNC, page 142-149. IEEE Computer Society, (2012)