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A 40 nm 144 mW VLSI processor for realtime 60 kWord continuous speech recognition.

G. He, T. Sugahara, T. Fujinaga, Y. Miyamoto, H. Noguchi, S. Izumi, H. Kawaguchi, and M. Yoshimoto. CICC, page 1-4. IEEE, (2011)

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Masahiko Isaji

Kei Yoshimoto

Other publications of authors with the same name

Normally Off ECG SoC With Non-Volatile MCU and Noise Tolerant Heartbeat Detector.S. Izumi, K. Yamashita, M. Nakano, S. Yoshimoto, T. Nakagawa, Y. Nakai, H. Kawaguchi, H. Kimura, K. Marumoto, T. Fuchikami and 4 other author(s). IEEE Trans. Biomed. Circuits Syst., 9 (5): 641-651 (2015)A half-pel precision MPEG2 motion-estimation processor with concurrent three-vector search.K. Ishihara, S. Masuda, S. ichi Hattori, H. Nishikawa, Y. Ajioka, T. Yamada, H. Amishiro, S. ichi Uramoto, M. Yoshimoto, and T. Sumi. IEEE J. Solid State Circuits, 30 (12): 1502-1509 (December 1995)Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential.H. Noguchi, Y. Iguchi, H. Fujiwara, S. Okumura, K. Nii, H. Kawaguchi, and M. Yoshimoto. IPSJ Trans. Syst. LSI Des. Methodol., (2011)A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM.Y. Umeki, K. Yanagida, S. Yoshimoto, S. Izumi, M. Yoshimoto, H. Kawaguchi, K. Tsunoda, and T. Sugii. IPSJ Trans. Syst. LSI Des. Methodol., (2016)A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme.G. Matsukawa, Y. Nakata, Y. Sugure, S. Oho, Y. Kimi, M. Shimozawa, S. Yoshida, H. Kawaguchi, and M. Yoshimoto. IEICE Trans. Electron., 98-C (4): 333-339 (2015)A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation.Y. Nakata, Y. Kimi, S. Okumura, J. Jung, T. Sawada, T. Toshikawa, M. Nagata, H. Nakano, M. Yabuuchi, H. Fujiwara and 4 other author(s). IEICE Trans. Electron., 97-C (4): 332-341 (2014)A 433-MHz Rail-to-Rail Voltage Amplifier with Carrier Sensing Function for Wireless Sensor Networks.T. Takeuchi, S. Mikami, H. Lee, H. Kawaguchi, C. Ohta, and M. Yoshimoto. IEICE Trans. Electron., 92-C (6): 815-821 (2009)Counter-Based Broadcasting with Hop Count Aware Random Assessment Delay Extension for Wireless Sensor Networks.S. Izumi, T. Takeuchi, T. Matsuda, H. Kawaguchi, C. Ohta, and M. Yoshimoto. IEICE Trans. Commun., 91-B (11): 3489-3498 (2008)Divided Static Random Access Memory for Data Aggregation in Wireless Sensor Nodes.T. Matsuda, S. Izumi, Y. Sakai, T. Takeuchi, H. Fujiwara, H. Kawaguchi, C. Ohta, and M. Yoshimoto. IEICE Trans. Commun., 95-B (1): 178-188 (2012)A Dependable SRAM with 7T/14T Memory Cells.H. Fujiwara, S. Okumura, Y. Iguchi, H. Noguchi, H. Kawaguchi, and M. Yoshimoto. IEICE Trans. Electron., 92-C (4): 423-432 (2009)

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Disambiguation of "Yoshimoto, Masahiko"

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A 40 nm 144 mW VLSI processor for realtime 60 kWord continuous speech recognition.

Please choose a person to relate this publication to

Masahiko Isaji

Kei Yoshimoto

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Yoshimoto, Masahiko"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 40 nm 144 mW VLSI processor for realtime 60 kWord continuous speech recognition.

Please choose a person to relate this publication to

Masahiko Isaji

Kei Yoshimoto

Other publications of authors with the same name

Disambiguation

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URL
DOI
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APA
Chicago
DIN 1505
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A 40 nm 144 mW VLSI processor for realtime 60 kWord continuous speech recognition.