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Optimal and Heuristic Approaches to Modulo Scheduling With Rational Initiation Intervals in Hardware Synthesis.

, , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (3): 614-627 (2022)

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Optimal and Heuristic Approaches to Modulo Scheduling With Rational Initiation Intervals in Hardware Synthesis., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (3): 614-627 (2022)Speeding Up Optimal Modulo Scheduling with Rational Initiation Intervals., , and . FPL, page 322-326. IEEE, (2022)Modulo Scheduling with Rational Initiation Intervals in Custom Hardware Design., , , and . ASP-DAC, page 568-573. IEEE, (2020)ILP-Based Modulo Scheduling and Binding for Register Minimization., , , , , and . FPL, page 265-271. IEEE Computer Society, (2018)Optimal Binding and Port Assignment for Loop Pipelining in High-Level Synthesis., , and . FPL, page 262-269. IEEE, (2022)Improving Energy Efficiency in Loop Pipelining by Rational-II Modulo Scheduling., , and . FCCM, page 1-2. IEEE, (2022)ScaLP: A Light-Weighted (MI)LP-Library., , , and . MBMV, Universität Tübingen, (2018)Isomorphic Subgraph-based Problem Reduction for Resource Minimal Modulo Scheduling., , , and . ReConFig, page 1-8. IEEE, (2019)Constant Matrix Multiplication with Ternary Adders., , , and . ICECS, page 85-88. IEEE, (2018)Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling., , , , , and . Euro-Par, volume 11725 of Lecture Notes in Computer Science, page 170-183. Springer, (2019)