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Disambiguation of "Yoshimoto, Masahiko"

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A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering.

, , , , , , and . ISLPED, page 61-66. ACM, (2006)

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Masahiko Isaji

Kei Yoshimoto

 

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A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM., , , , , , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2016)Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential., , , , , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2011)Divided Static Random Access Memory for Data Aggregation in Wireless Sensor Nodes., , , , , , , and . IEICE Trans. Commun., 95-B (1): 178-188 (2012)A Dependable SRAM with 7T/14T Memory Cells., , , , , and . IEICE Trans. Electron., 92-C (4): 423-432 (2009)A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer., , , , , , , , and . IEICE Trans. Electron., 91-C (4): 465-478 (2008)VLSI Architecture of GMM Processing and Viterbi Decoder for 60, 000-Word Real-Time Continuous Speech Recognition., , , , , and . IEICE Trans. Electron., 94-C (4): 458-467 (2011)A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme., , , , , , , , and . IEICE Trans. Electron., 98-C (4): 333-339 (2015)A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation., , , , , , , , , and 4 other author(s). IEICE Trans. Electron., 97-C (4): 332-341 (2014)A 433-MHz Rail-to-Rail Voltage Amplifier with Carrier Sensing Function for Wireless Sensor Networks., , , , , and . IEICE Trans. Electron., 92-C (6): 815-821 (2009)A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor., , , , , , and . IEICE Trans. Electron., 99-C (8): 901-908 (2016)