From post

A 12 bit 1 GS/s Dual-Rate Hybrid DAC With an 8 GS/s Unrolled Pipeline Delta-Sigma Modulator Achieving > 75 dB SFDR Over the Nyquist Band.

, , , и . IEEE J. Solid State Circuits, 50 (4): 896-907 (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

 

Другие публикации лиц с тем же именем

A 12 bit 1 GS/s Dual-Rate Hybrid DAC With an 8 GS/s Unrolled Pipeline Delta-Sigma Modulator Achieving > 75 dB SFDR Over the Nyquist Band., , , и . IEEE J. Solid State Circuits, 50 (4): 896-907 (2015)A 12-Bit 2 GS/s Dual-Rate Hybrid DAC With Pulse-Error Pre-Distortion and In-Band Noise Cancellation Achieving > 74 dBc SFDR and <-80 dBc IM3 up to 1 GHz in 65 nm CMOS., и . IEEE J. Solid State Circuits, 51 (12): 2963-2978 (2016)10.2 A SAW-Less Direct-Digital RF Modulator with Tri-Level Time-Approximation Filter and Reconfigurable Dual-Band Delta-Sigma Modulation., и . ISSCC, стр. 174-176. IEEE, (2020)From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning., , , , , , , , , и 5 other автор(ы). ICCAD, стр. 1-9. IEEE, (2021)Analog Kalman Filter with Integration and Digitization via a Shared Thyristor-Based VCO for Sensor Fusion in 65 nm CMOS., , , , , , , , , и 2 other автор(ы). ESSCIRC, стр. 213-216. IEEE, (2023)TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture., , , , , и . ASP-DAC, стр. 526-531. IEEE, (2022)A 16b 12GS/S single/dual-rate DAC with successive bandpass delta-sigma modulator achieving <-67dBc IM3 within DC-to-6GHz tunable passbands., и . ISSCC, стр. 362-364. IEEE, (2018)A Fractional-N Digital MDLL With Background Two-Point DTC Calibration., , , и . IEEE J. Solid State Circuits, 57 (1): 80-89 (2022)A 16-bit 12-GS/s Single-/Dual-Rate DAC With a Successive Bandpass Delta-Sigma Modulator Achieving <-67-dBc IM3 Within DC to 6-GHz Tunable Passbands., и . IEEE J. Solid State Circuits, 53 (12): 3517-3527 (2018)29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur., , , и . ISSCC, стр. 410-412. IEEE, (2021)