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A nonvolatile look-up table using ReRAM for reconfigurable logic.

W. Lin, S. Sheu, C. Kuo, P. Tseng, M. Chang, K. Su, C. Lin, K. Tsai, S. Lee, S. Liu, Y. Chen, H. Lee, C. Hsu, F. Chen, T. Ku, M. Tsai, and M. Kao. A-SSCC, page 133-136. IEEE, (2014)

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Li-heng Lee

Heiner Heng

Heng Li

Yi Heng

Nora Heng

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A nonvolatile look-up table using ReRAM for reconfigurable logic.W. Lin, S. Sheu, C. Kuo, P. Tseng, M. Chang, K. Su, C. Lin, K. Tsai, S. Lee, S. Liu and 7 other author(s). A-SSCC, page 133-136. IEEE, (2014)Metal-Oxide RRAM.H. Wong, H. Lee, S. Yu, Y. Chen, Y. Wu, P. Chen, B. Lee, F. Chen, and M. Tsai. Proc. IEEE, 100 (6): 1951-1970 (2012)Data retention statistics and modelling in HfO2 resistive switching memories.S. Ambrogio, S. Balatti, Z. Wang, Y. Chen, H. Lee, F. Chen, and D. Ielmini. IRPS, page 7. IEEE, (2015)Circuit Design Challenges in Computing-in-Memory for AI Edge Devices.X. Si, H. Qian, M. Chang, C. Xue, J. Su, Z. Zhang, S. Li, S. Sheu, H. Lee, P. Chen and 1 other author(s). ASICON, page 1-4. IEEE, (2019)15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips.J. Su, X. Si, Y. Chou, T. Chang, W. Huang, Y. Tu, R. Liu, P. Lu, T. Liu, J. Wang and 13 other author(s). ISSCC, page 240-242. IEEE, (2020)A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability.S. Sheu, M. Chang, K. Lin, C. Wu, Y. Chen, P. Chiu, C. Kuo, Y. Yang, P. Chiang, W. Lin and 12 other author(s). ISSCC, page 200-202. IEEE, (2011)A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes.M. Chang, S. Sheu, K. Lin, C. Wu, C. Kuo, P. Chiu, Y. Yang, Y. Chen, H. Lee, C. Lien and 5 other author(s). IEEE J. Solid State Circuits, 48 (3): 878-891 (2013)17.5 A 3T1R nonvolatile TCAM using MLC ReRAM with Sub-1ns search time.M. Chang, C. Lin, A. Lee, C. Kuo, G. Yang, H. Tsai, T. Chen, S. Sheu, P. Tseng, H. Lee and 1 other author(s). ISSCC, page 1-3. IEEE, (2015)NV-BNN: An Accurate Deep Convolutional Neural Network Based on Binary STT-MRAM for Adaptive AI Edge.C. Chang, M. Wu, J. Lin, C. Li, V. Parmar, H. Lee, J. Wei, S. Sheu, M. Suri, T. Chang and 1 other author(s). DAC, page 30. ACM, (2019)Analyzing inference robustness of RRAM synaptic array in low-precision neural network.R. Liu, H. Lee, and S. Yu. ESSDERC, page 18-21. IEEE, (2017)

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Disambiguation of "Lee, Heng-Yuan"

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A nonvolatile look-up table using ReRAM for reconfigurable logic.

Please choose a person to relate this publication to

Li-heng Lee

Heiner Heng

Heng Li

Yi Heng

Nora Heng

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Lee, Heng-Yuan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A nonvolatile look-up table using ReRAM for reconfigurable logic.

Please choose a person to relate this publication to

Li-heng Lee

Heiner Heng

Heng Li

Yi Heng

Nora Heng

Other publications of authors with the same name

Disambiguation

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URL
DOI
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APA
Chicago
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A nonvolatile look-up table using ReRAM for reconfigurable logic.