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Optimization of the maximum delay of global interconnects duringlayer assignment., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (4): 503-515 (2001)A predictive distributed congestion metric with application to technology mapping., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (5): 696-710 (2005)Repeater scaling and its impact on CAD., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (4): 451-463 (2004)On integrating power and signal routing for shield count minimization in congested regions., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (4): 437-445 (2003)A perturbation-aware noise convergence methodology for high frequency microprocessors., , , и . ASP-DAC, стр. 717-722. ACM Press, (2005)Crosstalk Minimization Using Wire Perturbations., и . DAC, стр. 100-103. ACM Press, (1999)Net weighting to reduce repeater counts during placement., , и . DAC, стр. 503-508. ACM, (2005)The scaling challenge: can correct-by-construction design help?, , , и . ISPD, стр. 51-58. ACM, (2003)A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs., , , , и . Euro-Par, Vol. I, том 1123 из Lecture Notes in Computer Science, стр. 828-831. Springer, (1996)An Accurate, Error-Tolerant, and Energy-Efficient Neural Network Inference Engine Based on SONOS Analog Memory., , , , , , , , , и 2 other автор(ы). IEEE Trans. Circuits Syst. I Regul. Pap., 69 (4): 1480-1493 (2022)