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Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices., , , и . SLIP@DAC, стр. 1:1-1:8. ACM, (2018)C-Mine: Data Mining of Logic Common Cases for Low Power Synthesis of Better-Than-Worst-Case Designs., , и . DAC, стр. 205:1-205:6. ACM, (2014)Throughput-oriented kernel porting onto FPGAs., , , , и . DAC, стр. 11:1-11:10. ACM, (2013)Optimality study of resource binding with multi-Vdds., , , и . DAC, стр. 580-585. ACM, (2006)Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation., , , , , и . DAC, стр. 7:1-7:6. ACM, (2016)Fast large-scale optimal power flow analysis for smart grid through network reduction., и . ASP-DAC, стр. 373-378. IEEE, (2014)Flexible transition metal dichalcogenide field-effect transistors: A circuit-level simulation study of delay and power under bending, process variation, and scaling., , и . ASP-DAC, стр. 761-768. IEEE, (2016)A SPICE-compatible model of graphene nano-ribbon field-effect transistors enabling circuit-level delay and power analysis under process variation., , , , , и . DATE, стр. 1789-1794. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Behavioral-level IP integration in high-level synthesis., , , и . FPT, стр. 172-175. IEEE, (2015)High-level synthesis with behavioral level multi-cycle path analysis., , , , и . FPL, стр. 1-8. IEEE, (2013)