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Disambiguation of "Fredeman, Gregory"

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4.1 22nm Next-generation IBM System z microprocessor.

, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)

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Robert Gregory

Isa Gregory

Gregory Kroon

Xaver Gregory

Gregory Okereke

 

Other publications of authors with the same name

An 800-MHz embedded DRAM with a concurrent refresh mode., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 40 (6): 1377-1387 (2005)4.1 22nm Next-generation IBM System z microprocessor., , , , , , , , , and 21 other author(s). ISSCC, page 1-3. IEEE, (2015)A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS., , , , , , , , , and 11 other author(s). IEEE J. Solid State Circuits, 44 (4): 1216-1226 (2009)IBM z15: Physical design improvements to significantly increase content in the same technology., , , , , , , , , and 10 other author(s). IBM J. Res. Dev., 64 (5/6): 8:1-8:12 (2020)17.4 A 14nm 1.1Mb embedded DRAM macro with 1ns access., , , , , , , , , and 4 other author(s). ISSCC, page 1-3. IEEE, (2015)Cores, Cache, Content, and Characterization: IBM's Second Generation 14-nm Product, z15., , , , , , , , , and 19 other author(s). IEEE J. Solid State Circuits, 56 (1): 98-111 (2021)A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access., , , , , , , , , and 12 other author(s). IEEE J. Solid State Circuits, 51 (1): 230-239 (2016)A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 46 (1): 64-75 (2011)A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 46 (1): 64-75 (2011)A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache., , , , , , , , , and . ISSCC, page 342-343. IEEE, (2010)