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Analysis of BTI in 300 mm integrated dual-gate WS2 FETs., , , , , , and . DRC, page 1-2. IEEE, (2022)Tunneling transistors based on MoS2/MoTe2 Van der Waals heterostructures., , , , , , , , , and 1 other author(s). ESSDERC, page 106-109. IEEE, (2017)Impact of gate stack processing on the hysteresis of 300 mm integrated WS2 FETs., , , , , , , , , and 2 other author(s). IRPS, page 1-6. IEEE, (2023)Beyond-Si materials and devices for more Moore and more than Moore applications., , , , , , , , , and 16 other author(s). ICICDT, page 1-5. IEEE, (2016)Towards low damage and fab-compatible top-contacts in MX2 transistors using a combined synchronous pulse atomic layer etch and wet-chemical etch approach., , , , , , , , , and 7 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)The Promise of 2-D Materials for Scaled Digital and Analog Applications., , , , , , , , , and 2 other author(s). ISSCC, page 394-395. IEEE, (2023)WS2 transistors on 300 mm wafers with BEOL compatibility., , , , , , , , , and 8 other author(s). ESSDERC, page 212-215. IEEE, (2017)Tunnel FETs using Phosphorene/ReS2 heterostructures., , , , , and . DRC, page 113-114. IEEE, (2019)Experimental calibration of the temperature dependence of the heterojunction bandgap in III-V tunneling devices., , , , and . DRC, page 253-254. IEEE, (2019)Integration of epitaxial monolayer MX₂ channels on 300mm wafers via Collective-Die-To-Wafer (CoD2W) transfer., , , , , , , , , and 10 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)