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Disambiguation of "Moreira, Matheus Trevisan"

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Performance Optimization and Analysis of Blade Designs under Delay Variability.

, , , , , , , and . ASYNC, page 61-68. IEEE Computer Society, (2015)

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Daniela Trevisan

Rüdiger Matheus

Enrico Trevisan

Jochen Matheus

Ricarda Matheus

 

Other publications of authors with the same name

Asynchronous circuits: innovations in components, cell libraries and design templates.. Pontifícia Universidade Católica do Rio Grande do Sul, Brazil, (2016)ndltd.org (oai:tede2.pucrs.br:tede/6635).Design and analysis of the HF-RISC processor targeting voltage scaling applications., , , , , , and . SBCCI, page 1-6. IEEE, (2016)Blade - A Timing Violation Resilient Asynchronous Template., , , , , , , , , and . ASYNC, page 21-28. IEEE Computer Society, (2015)A QDI Interconnect for 3D Systems Using Industry Standard EDA and Cell Libraries., , , , and . ASYNC, page 58-59. IEEE, (2023)Validating an Automated Asynchronous Synthesis Environment with a Challenging Design: RISC-V., , , , and . SBCCI, page 1-6. IEEE, (2023)A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework., , and . DSD, page 79-86. IEEE Computer Society, (2015)Chronos Link: A QDI Interconnect for Modern SoCs., and . ASYNC, page 67-68. IEEE, (2020)Hardening QDI circuits against transient faults using delay-insensitive maxterm synthesis., , , and . ACM Great Lakes Symposium on VLSI, page 3-8. ACM, (2014)Optimized Design of an LSSD Scan Cell., , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (2): 765-768 (2017)11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint., , , , , , , , , and 3 other author(s). ISSCC, page 210-212. IEEE, (2024)