( en | de | ru )

 

Disambiguation of "Calazans, Ney Laert Vilar"

Author of the publication

copydeleteadd this publication to your clipboard
Performance Optimization and Analysis of Blade Designs under Delay Variability.

, , , , , , , and . ASYNC, page 61-68. IEEE Computer Society, (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Loreto Vilar

Ignazio Vilardi

Fabio Vilardi

Sisi Alexandra Vilardi

David Vilar Torres

 

Other publications of authors with the same name

Return-to-one protocol for reducing static power in C-elements of QDI circuits employing m-of-n codes., , and . SBCCI, page 1-6. IEEE, (2012)A design flow for physical synthesis of digital cells with ASTRAN., , , , and . ACM Great Lakes Symposium on VLSI, page 245-246. ACM, (2014)The HF-RISC processor: Performance assessment., , , and . LASCAS, page 95-98. IEEE, (2016)Rate-based scheduling policy for QoS flows in networks on chip., and . VLSI-SoC, page 140-145. IEEE, (2007)Evaluating the robustness of secure triple track logic through prototyping., , , , , and . SBCCI, page 193-198. ACM, (2008)Automated Synthesis of Cell Libraries for Asynchronous Circuits., , , , and . SBCCI, page 16:1-16:7. ACM, (2014)Design and analysis of the HF-RISC processor targeting voltage scaling applications., , , , , , and . SBCCI, page 1-6. IEEE, (2016)Design and Analysis of Testable Mutual Exclusion Elements., , , , , , and . ASYNC, page 124-131. IEEE Computer Society, (2015)Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications., , , , , and . ASYNC, page 11-18. IEEE Computer Society, (2016)Blade - A Timing Violation Resilient Asynchronous Template., , , , , , , , , and . ASYNC, page 21-28. IEEE Computer Society, (2015)