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SLS-a fast switch-level simulator for MOS.

, , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 7 (8): 838-849 (1988)

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Marc Huisman

Leendert Bliek

Leendert Molendijk

Leendert Euser

Brent Huisman

 

Другие публикации лиц с тем же именем

SLS - a fast switch level simulator for verification and fault coverage analysis., , , , и . DAC, стр. 164-170. IEEE Computer Society Press, (1986)The reliability of approximate testability measures.. IEEE Des. Test, 5 (6): 57-67 (1988)Using a Hardware Simulation Engine for Custom MOS Structured Designs., , , и . IBM J. Res. Dev., 28 (5): 564-571 (1984)Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm., , , и . ITC, стр. 287-296. IEEE Computer Society, (2001)Analysis and Design of Optimal Combinational Compactors., и . VTS, стр. 101-106. IEEE Computer Society, (2003)Fault simulation of logic designs on parallel processors with distributed memory., и . ITC, стр. 690-697. IEEE Computer Society, (1990)Diagnosis and characterization of timing-related defects by time-dependent light emission., , , , , , , , , и 1 other автор(ы). ITC, стр. 733-739. IEEE Computer Society, (1998)Correlations between path delays and the accuracy of performance prediction.. ITC, стр. 801-808. IEEE Computer Society, (1998)TRIM: testability range by ignoring the memory., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 7 (1): 38-49 (1988)A Small Test Generator for Large Designs., , , , и . ITC, стр. 30-40. IEEE Computer Society, (1992)