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Multi-subregion based probabilistic approach toward pose-invariant face recognition., and . CIRA, page 954-959. IEEE, (2003)A Calculus of Testability Measure at the Functional Level., , , and . ITC, page 95-101. IEEE Computer Society, (1981)A design method of multidimensional linear-phase paraunitary filter banks with a lattice structure., , and . IEEE Trans. Signal Process., 47 (3): 690-700 (1999)Logic simulation engines in Japan., , and . IEEE Des. Test, 6 (5): 40-49 (1989)Hierarchical design verification for large digital systems., , , , , and . DAC, page 105-112. ACM/IEEE, (1981)MIXS: A mixed level simulator for large digital system logic verification., , , , , and . DAC, page 626-633. ACM/IEEE, (1980)Automatic System Level Test Generation and Fault Location for Large Digital Systems., , , and . DAC, page 347-352. ACM, (1978)Automatic test generation for large digital circuits., , , , , and . DAC, page 78-83. ACM, (1977)A design method for oversampled paraunitary DFT filter banks using householder factorization., , , , and . EUSIPCO, page 1-4. IEEE, (1996)MDS: An improved total system for firmware development., , , , and . MICRO, page 50-56. ACM/IEEE, (1982)