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pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking.

Y. Kim, H. Kwon, S. Doo, M. Ahn, Y. Kim, Y. Lee, D. Kang, S. Do, C. Lee, G. hee Cho, J. Park, J. Kim, K. Park, S. Oh, S. Lee, J. Yu, K. Yu, C. Jeon, S. Kim, H. Park, J. Lee, S. Cho, K. Park, Y. Kim, Y. Seo, C. Shin, C. Lee, S. Bang, Y. Park, S. Choi, B. Kim, G. Han, S. Bae, H. Kwon, J. Choi, Y. Sohn, K. Park, S. Jang, and G. Jin. IEEE J. Solid State Circuits, 54 (1): 197-209 (2019)

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Seung Sung Oh

Seung-Eun Oh

Seong-Hoon Oh

Seung-Koo Oh

Seung Cheol Oh

Other publications of authors with the same name

The Wide Input Range Automatic-Threshold Control Circuit for High Definition Digital Audio Interface.J. Jeong, G. Kim, S. Oh, K. Kim, and S. Kim. ISCAS, page 2558-2561. IEEE, (2007)Coherent single-atom superradianceJ. Kim, D. Yang, S. Oh, and K. An. Science, 359 (6376): 662--666 (2018)A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking.Y. Kim, H. Kwon, S. Doo, Y. Eom, Y. Kim, M. Ahn, Y. Kim, S. Jung, S. Do, C. Lee and 39 other author(s). ISSCC, page 204-206. IEEE, (2018)A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation.T. Oh, H. Chung, J. Park, K. Lee, S. Oh, S. Doo, H. Kim, C. Lee, H. Kim, J. Lee and 10 other author(s). IEEE J. Solid State Circuits, 50 (1): 178-190 (2015)A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process.D. Kim, B. Song, H. Ahn, W. Ko, S. Do, S. Cho, K. Kim, S. Oh, H. Joo, G. Park and 37 other author(s). ISSCC, page 448-450. IEEE, (2022)A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking.Y. Kim, H. Kwon, S. Doo, M. Ahn, Y. Kim, Y. Lee, D. Kang, S. Do, C. Lee, G. hee Cho and 29 other author(s). IEEE J. Solid State Circuits, 54 (1): 197-209 (2019)3D femoral neck anteversion measurements based on the posterior femoral plane in ORTHODOC® system.Y. Lee, S. Oh, J. Seon, E. Song, and T. Yoon. Medical Biol. Eng. Comput., 44 (10): 895-906 (2006)Characteristics of solderable electrically conductive adhesives (ECAs) for electronic packaging.B. seung Yim, Y. Kwon, S. Oh, J. Kim, Y. Shin, S. Lee, and J. Kim. Microelectron. Reliab., 52 (6): 1165-1173 (2012)3D femoral neck anteversion measurements based on the posterior femoral plane in ORTHODOC® system.Y. Lee, S. Oh, J. Seon, E. Song, and T. Yoon. Medical Biol. Eng. Comput., 45 (3): 325 (2007)

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Disambiguation of "Oh, Seung-Hoon"

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A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking.

Please choose a person to relate this publication to

Seung Sung Oh

Seung-Eun Oh

Seong-Hoon Oh

Seung-Koo Oh

Seung Cheol Oh

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Oh, Seung-Hoon"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking.

Please choose a person to relate this publication to

Seung Sung Oh

Seung-Eun Oh

Seong-Hoon Oh

Seung-Koo Oh

Seung Cheol Oh

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking.