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Disambiguation of "Diaz, Carlos H."

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Exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design.

, , , , , and . IEEE J. Solid State Circuits, 36 (10): 1480-1488 (2001)

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Carlos Diaz Cascajo

Carlos Contreras H

Carlos Enrique Gorbea Díaz

Carlos Enrique Gorbea Díaz

Gonzalo Díaz Díaz

 

Other publications of authors with the same name

Correction to "exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design"., , , , , and . IEEE J. Solid State Circuits, 37 (2): 255 (2002)Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 13 (4): 482-493 (1994)A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics., , , , , , , , , and 1 other author(s). CICC, page 245-248. IEEE, (2003)Challenges toward Low-Power SOT-MRAM., , , , , , , , , and 5 other author(s). IRPS, page 1-7. IEEE, (2021)28nm metal-gate high-K CMOS SoC technology for high-performance mobile applications., , , , , , , , , and 23 other author(s). CICC, page 1-5. IEEE, (2011)Thermal Failure Simulation for Electrical Overstress in Semiconductor Devices., , and . ISCAS, page 1389-1392. IEEE, (1993)Process and circuit design interlock for application-dependent scaling tradeoffs and optimization in the SoC era., , , and . IEEE J. Solid State Circuits, 38 (3): 444-449 (2003)Exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design., , , , , and . IEEE J. Solid State Circuits, 36 (10): 1480-1488 (2001)Application-dependent scaling tradeoffs and optimization in the SoC era., , , and . CICC, page 475-478. IEEE, (2002)Device trends and implications on circuit design in advanced CMOS technologies., , , , , , , , , and 1 other author(s). CICC, page 675-679. IEEE, (2005)