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On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines.. J. Electron. Test., 22 (4-6): 387-398 (2006)LPTest: a Flexible Low-Power Test Pattern Generator., , и . J. Electron. Test., 25 (6): 323-335 (2009)Diagnosing integrator leakage of single-bit first-order DeltaSigma modulator using DC input., , и . ASP-DAC, стр. 775-780. IEEE, (2009)Practical considerations in applying Σ-Δ modulation-based analog BIST to sampled-data systems., , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 50 (9): 553-566 (2003)A SAR ADC missing-decision level detection and removal technique., , , и . VTS, стр. 31-36. IEEE Computer Society, (2012)An Efficient Peak Power Reduction Technique for Scan Testing., , и . ATS, стр. 111-114. IEEE, (2007)BDD-Based Self-Test Program Generation for Processor Cores., , , и . ITC-Asia, стр. 1-6. IEEE, (2023)Automatic Test Program Generation for Transition Delay Faults in Pipelined Processors., , , , и . ITC-Asia, стр. 1-6. IEEE, (2021)An On-Chip Integrator Leakage Characterization Technique and Its Application to Switched Capacitor Circuits Testing., , и . Asian Test Symposium, стр. 367-372. IEEE Computer Society, (2009)A Low-Cost Jitter Measurement Technique for BIST Applications., и . Asian Test Symposium, стр. 336-339. IEEE Computer Society, (2003)