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A 3.9-fJ/c.-s. 0.5-V 10-bit 100-kS/s low power SAR ADC with time-based fixed window.

, , , and . ISCAS, page 2345-2348. IEEE, (2014)

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A 0.9-V 11-bit 25-MS/s binary-search SAR ADC in 90-nm CMOS., , , , and . A-SSCC, page 69-72. IEEE, (2011)A pipelined SAR ADC with loading-separating technique in 90-nm CMOS technology., , , and . APCCAS, page 264-267. IEEE, (2012)A power-efficient sizing methodology of SAR ADCs., , , and . ISCAS, page 365-368. IEEE, (2012)A 3.9-fJ/c.-s. 0.5-V 10-bit 100-kS/s low power SAR ADC with time-based fixed window., , , and . ISCAS, page 2345-2348. IEEE, (2014)A successive approximation ADC with resistor-capacitor hybrid structure., , and . VLSI-DAT, page 1-4. IEEE, (2013)A Low-Cost Bit-Error-Rate BIST Circuit for High-Speed ADCs Based on Gray Coding., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 95-A (12): 2415-2423 (2012)A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications., , , and . IEEE J. Solid State Circuits, 47 (11): 2783-2795 (2012)A 10b 100kS/s SAR ADC with charge recycling switching method., , , and . A-SSCC, page 329-332. IEEE, (2014)Federated Learning Architecture for Bearing Fault Diagnosis., and . ICSSE, page 408-411. IEEE, (2021)A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (3): 570-581 (2013)