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Systematic Application of Data Transfer and Storage Optimizing Code Transformations for Power Consumption and Execution Time Reduction in ACROPOLIS: A Pre-Compiler for Multimedia Applications.

, , , and . Des. Autom. Embed. Syst., 8 (1): 51-86 (2003)

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Performance Through Hierarchy in Static Timing Verification., , and . IFIP Congress (1), volume A-12 of IFIP Transactions, page 703-709. North-Holland, (1992)Static Timing Analysis of Dynamically Sensitizable Paths., , and . DAC, page 568-573. ACM Press, (1989)Loop Optimization in Register-Transfer Scheduling for DSP-Systems., , and . DAC, page 826-831. ACM Press, (1989)Efficient computation of symbol statistics from bit a priori information in turbo receivers., , , , and . IEEE Trans. Commun., 57 (7): 1889-1891 (2009)Reed-solomon codes implementing a coded single-carrier with cyclic prefix scheme., , and . IEEE Trans. Commun., 57 (4): 1031-1038 (2009)Partial scan and symbolic test at the register-transfer level., , and . J. Electron. Test., 7 (1-2): 7-23 (1995)Panel session - great challenges in nanoelectronics and impact on academic research: More than Moore or Beyond CMOS?, , , , , , and . DATE, page 1677. IEEE Computer Society, (2010)Systematic Application of Data Transfer and Storage Optimizing Code Transformations for Power Consumption and Execution Time Reduction in ACROPOLIS: A Pre-Compiler for Multimedia Applications., , , and . Des. Autom. Embed. Syst., 8 (1): 51-86 (2003)Timing verification using statically sensitizable paths., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 9 (10): 10723-10784 (1990)Cellular automata based deterministic self-test strategies for programmable data paths., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 13 (7): 940-949 (1994)