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An efficient motion estimation hardware architecture using Modified Reference Data Access(MRDAS) skip algorithm for high Efficiency Video Coding(HEVC) encoder., , , , и . ICCE-Berlin, стр. 85-89. IEEE, (2016)Multi-core platform for an efficient H.264 and VC-1 video decoding based on macroblock row-level parallelism., , и . IET Circuits Devices Syst., 4 (2): 147-158 (2010)Image compression based on MR-CNN (Modified Region Convolutional Neural Network)., , , , , , и . ISOCC, стр. 292-293. IEEE, (2017)A 166.7 Mhz 1920×1080 60fps H.264/SVC video decoder., , и . ISOCC, стр. 278-281. IEEE, (2011)Fast decision of CU partitioning based on SAO parameter, motion and PU/TU split information for HEVC., , и . PCS, стр. 113-116. IEEE, (2013)A MPEG-4 Video Codec Chip with Low Power Scheme for Mobile Application., , , , , и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 86-A (6): 1353-1363 (2003)A 100MHz ASIP (application specific instruction processor) for CAVLC of H.264/AVC decoder., , , , и . ISCAS, стр. 3462-3465. IEEE, (2008)An efficient architecture of DCTQ module in MPEG-4 video codec., , , , , , и . ISCAS (1), стр. 777-780. IEEE, (2002)An Efficient Architecture of In-Loop Filters for Multicore Scalable HEVC Hardware Decoders., , и . IEEE Trans. Multim., 20 (4): 810-824 (2018)Selective clock gating by using wasting toggle rate., , , и . EIT, стр. 399-404. IEEE, (2009)