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Disambiguation of "Hu, Vita Pi-Ho"

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Improved Read Stability and Writability of Negative Capacitance FinFET SRAM Cell for Subthreshold Operation.

, and . ISCAS, page 1-5. IEEE, (2019)

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Gerhard Vita

Vita Paliokaite

Vita Graudins

Vita Feldmann

Vita Kondratenko

 

Other publications of authors with the same name

Device Designs and Analog Performance Analysis for Negative-Capacitance Vertical-Tunnel FET., and . ISQED, page 241-246. IEEE, (2019)Ultra-low voltage mixed TFET-MOSFET 8T SRAM cell., , , , and . ISLPED, page 255-258. ACM, (2014)A comparative analysis of tunneling FET circuit switching characteristics and SRAM stability and performance., , , , , , and . ESSDERC, page 157-160. IEEE, (2012)Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (12): 3339-3347 (2014)Impacts of NBTI and PBTI on ultra-thin-body GeOI 6T SRAM cells., , , and . ISCAS, page 601-604. IEEE, (2015)Evaluation of TFET and FinFET devices and 32-Bit CLA circuits considering work function variation and line-edge roughness., , , , , and . ISCAS, page 2325-2328. IEEE, (2015)Monolithic 3D SRAM Cell with Stacked Two-Dimensional Materials Based FETs at 2nm Node., , , , and . ISCAS, page 1-5. IEEE, (2021)Evaluation of Read- and Write-Assist circuits for GeOI FinFET 6T SRAM cells., , , and . ISCAS, page 1122-1125. IEEE, (2014)Stability and performance optimization of InGaAs-OI and GeOI hetero-channel SRAM cells., , , and . ESSDERC, page 77-80. IEEE, (2012)Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits., , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 4 (4): 389-399 (2014)