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Disambiguation of "Fujiwara, Hideo"

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A DFT Method for Time Expansion Model at Register Transfer Level.

, , and . DAC, page 682-687. IEEE, (2007)

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Esther Fujiwara

Hideo Baba

Hideo Ohashi

Hideo Andreas Baba

Hideo Ikezawa-Hanada

 

Other publications of authors with the same name

Optimal Wait-Free Clock Synchronisation Protocol on a Shared-Memory Multi-processor System., , , and . WDAG, volume 1320 of Lecture Notes in Computer Science, page 290-304. Springer, (1997)Brief Announcement: Acceleration by Contention for Shared Memory Mutual Exclusion Algorithms., , and . DISC, volume 5805 of Lecture Notes in Computer Science, page 172-173. Springer, (2009)New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency., , and . J. Electron. Test., 20 (3): 315-323 (2004)Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption., , and . J. Electron. Test., 18 (1): 55-62 (2002)Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints., , , , , and . J. Electron. Test., 28 (4): 511-521 (2012)SPIRIT: a highly robust combinational test generation algorithm., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (12): 1446-1458 (2002)Handling the pin overhead problem of DFTs for high-quality and at-speed tests., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (9): 1105-1113 (2002)A Test Generation Method Based on k-Cycle Testing for Finite State Machines., , and . IOLTS, page 232-235. IEEE, (2019)Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation., , and . VLSI-SoC (Selected Papers), volume 249 of IFIP, page 301-316. Springer, (2006)Test pattern selection to optimize delay test quality with a limited size of test set., , , , and . European Test Symposium, page 260. IEEE Computer Society, (2010)