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Disambiguation of "Pan, David Z."

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DREAMPlaceFPGA: An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit.

, , , , and . ASP-DAC, page 300-306. IEEE, (2022)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

David Tse-chien Pan

Z Taufig

Xiaoqing Pan

Petra Pan

Weiqing Pan

 

Other publications of authors with the same name

Editorial: ACM Transactions on Design Automation of Electronics Systems and Beyond., , and . ACM Trans. Design Autom. Electr. Syst., 20 (1): 1:1-1:2 (2014)BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability., , , and . ACM Trans. Design Autom. Electr. Syst., 14 (2): 32:1-32:21 (2009)Total power optimization combining placement, sizing and multi-Vt through slack distribution management., , and . ASP-DAC, page 352-357. IEEE, (2008)BOB-router: A new buffering-aware global router with over-the-block routing resources optimization., , and . ASP-DAC, page 513-518. IEEE, (2014)Self-aligned double patterning layout decomposition with complementary e-beam lithography., , and . ASP-DAC, page 143-148. IEEE, (2014)Layout-dependent aging mitigation for critical path timing., , , , , , , and . ASP-DAC, page 153-158. IEEE, (2018)Machine learning and pattern matching in physical design., , , and . ASP-DAC, page 286-293. IEEE, (2015)A high-performance triple patterning layout decomposer with balanced density., , , , , and . ICCAD, page 163-169. IEEE, (2013)Global Routing., and . Encyclopedia of Algorithms, (2016)Machine learning for IC design and technology co-optimization in extreme scaling.. VLSI-DAT, page 1. IEEE, (2018)