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Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations., , и . ICCAD, стр. 736-741. IEEE Computer Society, (2005)Characterization of NBTI induced temporal performance degradation in nano-scale SRAM array using IDDQ., , и . ITC, стр. 1-10. IEEE Computer Society, (2007)Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement., , , , и . DAC, стр. 358-363. IEEE, (2007)Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop., , и . DAC, стр. 934-939. IEEE, (2007)Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance., , , и . ICCAD, стр. 730-734. IEEE Computer Society, (2007)Effectiveness of low power dual-Vt designs in nano-scale technologies under process parameter variations., , , , и . ISLPED, стр. 14-19. ACM, (2005)Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI., , , и . ICCD, стр. 216-221. IEEE, (2006)NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution?, , , и . ASP-DAC, стр. 726-731. IEEE, (2008)Fast and accurate estimation of nano-scaled SRAM read failure probability using critical point sampling., , , , и . CICC, стр. 439-442. IEEE, (2005)Reliable and self-repairing SRAM in nano-scale technologies using leakage and delay monitoring., , , и . ITC, стр. 10. IEEE Computer Society, (2005)