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A Physically Unclonable Function Using Time-to-Digital Converter with Linearity Self-Calibration and its FPGA Implementation., , , , , , , , , и 3 other автор(ы). ITC-Asia, стр. 1-6. IEEE, (2023)Fault Tolerant SoC Architecture Design for JPEG2000 Using Partial Reconfigurability., , и . DFT, стр. 31-40. IEEE Computer Society, (2007)Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability., , и . Inf. Media Technol., 3 (4): 704-716 (2008)Design for Delay Fault Testability of 2-Rail Logic Circuits., , и . IEICE Trans. Inf. Syst., 92-D (2): 336-341 (2009)A Delay Measurement Technique Using Signature Registers., , , , и . Asian Test Symposium, стр. 157-162. IEEE Computer Society, (2009)An Analysis of Stochastic Self-Calibration of TDC Using Two Ring Oscillators., , , , , и . Asian Test Symposium, стр. 140-146. IEEE Computer Society, (2013)Innovative Practices Track: Innovative Analog Circuit Testing Technologies., , , , , , , , , и 8 other автор(ы). VTS, стр. 1. IEEE, (2022)Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift., , и . IOLTS, стр. 203-204. IEEE Computer Society, (2005)Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices., и . ETS, стр. 69-74. IEEE Computer Society, (2006)A low area calibration technique of TDC using variable clock generator for accurate on-line delay measurement., и . ISQED, стр. 430-434. IEEE, (2015)