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Disambiguation of "Mohanty, Abinash"

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Parallel Programming of Resistive Cross-point Array for Synaptic Plasticity.

, , , , , , , , , and . BICA, volume 41 of Procedia Computer Science, page 126-133. Elsevier, (2014)

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Abinash Banerji

Jitendranath Mohanty

Subhasis Mohanty

Sasank Sekhar Mohanty

Abinash Chandra Chatterji

 

Other publications of authors with the same name

Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration., , , , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 5 (2): 194-204 (2015)RTN in Scaled Transistors for On-Chip Random Seed Generation., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (8): 2248-2257 (2017)Algorithm and Hardware Design for Efficient Deep Learning Inference.. Arizona State University, Tempe, USA, (2018)base-search.net (ftarizonastateun:item:51790).End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression., , , , , , , , , and . FPL, page 76-82. IEEE, (2021)Towards a Wearable Cough Detector Based on Neural Networks., , , , , , , , , and 3 other author(s). ICASSP, page 2161-2165. IEEE, (2018)Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks., , , , , , , and . FPGA, page 16-25. ACM, (2016)A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS., , , , , , , , and . ISCAS, page 1-4. IEEE, (2017)Towards Efficient Neural Networks On-a-chip: Joint Hardware-Algorithm Approaches., , , , , and . CoRR, (2019)A Real-Time 17-Scale Object Detection Accelerator With Adaptive 2000-Stage Classification in 65 nm CMOS., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (10): 3843-3853 (2019)Duty cycle shift under static/dynamic aging in 28nm HK-MG technology., , , , , , and . IRPS, page 7. IEEE, (2015)