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Disambiguation of "Kadetotad, Deepak"

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Parallel Programming of Resistive Cross-point Array for Synaptic Plasticity.

, , , , , , , , , and . BICA, volume 41 of Procedia Computer Science, page 126-133. Elsevier, (2014)

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Deepak Ajwani

Deepak Bararia

Deepak Jain

Deepak Samuel

Deepak Mathaikutty

 

Other publications of authors with the same name

A 8.93-TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity With All Parameters Stored On-Chip., , , and . ESSCIRC, page 119-122. IEEE, (2019)A Real-Time 17-Scale Object Detection Accelerator With Adaptive 2000-Stage Classification in 65 nm CMOS., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (10): 3843-3853 (2019)Comprehensive Evaluation of OpenCL-Based CNN Implementations for FPGAs., , , , , and . IWANN (2), volume 10306 of Lecture Notes in Computer Science, page 271-282. Springer, (2017)Compressing LSTM Networks with Hierarchical Coarse-Grain Sparsity., , , , and . INTERSPEECH, page 21-25. ISCA, (2020)Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip., , , , , , , , , and . DATE, page 854-859. ACM, (2015)An 8.93 TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity for On-Device Speech Recognition., , , , and . IEEE J. Solid State Circuits, 55 (7): 1877-1887 (2020)Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration., , , , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 5 (2): 194-204 (2015)Efficient memory compression in deep neural networks using coarse-grain sparsification for speech applications., , , and . ICCAD, page 78. ACM, (2016)A 1.06- $\mu$ W Smart ECG Processor in 65-nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring., , , , , , , and . IEEE J. Solid State Circuits, 54 (8): 2316-2326 (2019)A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV, and SRAM PUF for Authentication and Secret Key Generation., , , , , and . IEEE J. Solid State Circuits, 55 (10): 2680-2690 (2020)