( en | de | ru )

 

Disambiguation of "Hwang, TingTing"

Author of the publication

copydeleteadd this publication to your clipboard
Timing Aware Wrapper Cells Reduction for Pre-bond Testing in 3D-ICs.

, , , and . SoCC, page 236-241. IEEE, (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Tingting Wu

Tingting Xu

Tingting Han

Tingting Wen

Tingting Cui

 

Other publications of authors with the same name

A bus architecture for crosstalk elimination in high performance processor design., , and . CODES+ISSS, page 247-252. ACM, (2006)A functionality-directed clustering technique for low-power MTCMOS design - computation of simultaneously discharging current., , , and . ACM Trans. Design Autom. Electr. Syst., 12 (3): 30:1-30:25 (2007)New spare cell design for IR drop minimization in Engineering Change Order., , and . DAC, page 402-407. ACM, (2009)Architectural evaluations on TSV redundancy for reliability enhancement., , , and . DATE, page 566-571. IEEE, (2017)Switching-activity driven gate sizing and Vth assignment for low power design., , and . ASP-DAC, page 576-581. IEEE, (2006)Performance-driven interconnection optimization for microarchitecture synthesis., , , and . EURO-DAC, page 118-123. IEEE Computer Society Press, (1992)Performance-driven crosstalk elimination at post-compiler level., , , and . ISCAS, IEEE, (2006)Multi-Level Logic Synthesis Using Communication Complexity., , and . DAC, page 215-220. ACM Press, (1989)Combining technology mapping and placement for delay-minimization in FPGA designs., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (9): 1076-1084 (1995)On determining sensitization criterion in an iterative gate sizing process., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (2): 231-238 (1999)