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Disambiguation of "Raja, Tezaswi"

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CMOS Circuit Design for Minimum Dynamic Power and Highest Speed.

, , and . VLSI Design, page 1035-1040. IEEE Computer Society, (2004)

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Raja Paul

Raja Haddad

Sathishkumar Raja

Raja Silberkweit

Raja Biswas

 

Other publications of authors with the same name

A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET., , , , , , , , , and . ASYNC, page 27-35. IEEE, (2019)Digital Logic Implementation in Memristor-Based Crossbars - A Tutorial., and . DELTA, page 303-309. IEEE Computer Society, (2010)A Tuturial on the Emerging Nanotechnology Devices., , and . VLSI Design, page 343-360. IEEE Computer Society, (2004)Transistor Sizing of Logic Gates to Maximize Input Delay Variability., , and . J. Low Power Electron., 2 (1): 121-128 (2006)Variable Input Delay CMOS Logic for Low Power Design., , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (10): 1534-1545 (2009)Design of Variable Input Delay Gates for Low Dynamic Power Circuits., , and . PATMOS, volume 3728 of Lecture Notes in Computer Science, page 436-445. Springer, (2005)Variable Input Delay CMOS Logic for Low Power Design., , and . VLSI Design, page 598-605. IEEE Computer Society, (2005)An Energy-Recovering Reconfigurable Series Resonant Clocking Scheme for Wide Frequency Operation., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (7): 1766-1775 (2015)Low power low voltage wide frequency resonant clock and data circuits for power reductions., , , and . LASCAS, page 1-4. IEEE, (2013)Using a Jini based desktop Grid for test vector compaction and a refined economic model., and . CCGRID, page 798-805. IEEE Computer Society, (2004)