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Disambiguation of "Chang, Hsie-Chia"

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Improved High Code-Rate Soft BCH Decoder Architectures With One Extra Error Compensation.

, , and . IEEE Trans. Very Large Scale Integr. Syst., 21 (11): 2160-2164 (2013)

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Sheng-Chia Chang

William Ockham's view on human capability. Uni Frankfurt Main, (2009)

Chia-Ling Chang

Chia-Pin Chang

Chia-Yin Chang

Chia-Tche Chang

 

Other publications of authors with the same name

An Area-Efficient High-Throughput SM4 Accelerator with SCA-Countermeasure for TV Applications., , and . ISCAS, page 1-5. IEEE, (2020)Adjusted robust Soliton distribution (ARSD) with reshaped ripple size for LT codes., , , and . WCSP, page 1-6. IEEE, (2013)A Universal VLSI Architecture for Reed-Solomon Error-and-Erasure Decoders., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (9): 1960-1967 (2009)Generalized Globally-Coupled Low-Density Parity-Check Codes., , and . ITW, page 1-5. IEEE, (2018)Iterative Decoding Algorithms for a Class of Non-Binary Two-Step Majority-Logic Decodable Cyclic Codes., and . IEEE Trans. Commun., 62 (6): 1779-1789 (2014)A 26.9 K 314.5 Mb/s Soft (32400, 32208) BCH Decoder Chip for DVB-S2 System., , , and . IEEE J. Solid State Circuits, 45 (11): 2330-2340 (2010)A low power turbo/Viterbi decoder for 3GPP2 applications., , , and . IEEE Trans. Very Large Scale Integr. Syst., 14 (4): 426-430 (2006)A 3.46 Gb/s (9141, 8224) LDPC-based ECC scheme and on-line channel estimation for solid-state drive applications., , , , and . ISCAS, page 1450-1453. IEEE, (2015)A self-compensation fixed-width booth multiplier and its 128-point FFT applications., , and . ISCAS, IEEE, (2006)Area-efficient TFM-based stochastic decoder design for non-binary LDPC codes., , , , and . ISCAS, page 409-412. IEEE, (2014)