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An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS.

M. Ferriss, J. Plouchart, A. Natarajan, A. Rylyakov, B. Parker, A. Babakhani, S. Yaldiz, B. Sadhu, A. Valdes-Garcia, J. Tierno, and D. Friedman. VLSIC, page 176-177. IEEE, (2012)

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Maria-Draga Soneriu

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A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology.A. Lotfy, S. Farooq, Q. Wang, S. Yaldiz, P. Mosalikanti, and N. Kurd. CICC, page 1-4. IEEE, (2015)Analog/Mixed-Signal Layout Optimization using Optimal Well Taps.R. S, M. Madhusudan, A. Sharma, J. Poojary, S. Yaldiz, R. Harjani, S. Burns, and S. Sapatnekar. ISPD, page 159-166. ACM, (2022)Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits.A. Sharma, M. Madhusudan, S. Burns, S. Yaldiz, P. Mukherjee, R. Harjani, and S. Sapatnekar. ICCAD, page 1-9. IEEE, (2021)Analog Layout Automation On Advanced Process Technologies.S. Yaldiz. ISPD, page 103. ACM, (2023)Efficient statistical analysis of read timing failures in SRAM circuits.S. Yaldiz, U. Arslan, X. Li, and L. Pileggi. ISQED, page 617-621. IEEE Computer Society, (2009)An Integral Path Self-Calibration Scheme for a Dual-Loop PLL.M. Ferriss, J. Plouchart, A. Natarajan, A. Rylyakov, B. Parker, J. Tierno, A. Babakhani, S. Yaldiz, A. Valdes-Garcia, B. Sadhu and 1 other author(s). IEEE J. Solid State Circuits, 48 (4): 996-1008 (2013)A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement.T. Dhar, R. S, J. Poojary, S. Yaldiz, S. Burns, R. Harjani, and S. Sapatnekar. DATE, page 148-153. IEEE, (2022)An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS.M. Ferriss, J. Plouchart, A. Natarajan, A. Rylyakov, B. Parker, A. Babakhani, S. Yaldiz, B. Sadhu, A. Valdes-Garcia, J. Tierno and 1 other author(s). VLSIC, page 176-177. IEEE, (2012)Indirect phase noise sensing for self-healing voltage controlled oscillators.S. Yaldiz, V. Calayir, X. Li, L. Pileggi, A. Natarajan, M. Ferriss, and J. Tierno. CICC, page 1-4. IEEE, (2011)SRAM parametric failure analysis.J. Wang, S. Yaldiz, X. Li, and L. Pileggi. DAC, page 496-501. ACM, (2009)

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An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS.

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Maria-Draga Soneriu

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Disambiguation of "Yaldiz, Soner"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS.

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Soner Bulut

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Maria-Draga Soneriu

Soner Özen

Soner Aksu

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Disambiguation

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An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS.