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A scalable and near-optimal representation of access schemes for memory management.

, , , and . ACM Trans. Archit. Code Optim., 11 (1): 13:1-13:25 (2014)

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Performance Improvements in Microprocessor Systems Utilizing a Copressor Data-Path., , and . ICSAMOS, page 85-92. IEEE, (2006)A high-throughput and memory efficient 2D discrete wavelet transform hardware architecture for JPEG2000 standard., , , and . ISCAS (1), page 472-475. IEEE, (2005)On the computation of the prime factor DST., , , and . Signal Process., 42 (3): 231-236 (1995)Performance and Energy Consumption Improvements in Microprocessor Systems Utilizing a Coprocessor Data-Path., , and . J. Signal Process. Syst., 50 (2): 179-200 (2008)On the exploitation of a high-throughput SHA-256 FPGA design for HMAC., , , , and . ACM Trans. Reconfigurable Technol. Syst., 5 (1): 2:1-2:28 (2012)High-performance FPGA implementations of the cryptographic hash function JH., , , and . IET Comput. Digit. Tech., 7 (1): 29-40 (2013)A bit-serial VLSI architecture for the 2-D discrete cosine transform., and . Microprocess. Microprogramming, 40 (10-12): 829-832 (1994)Exploring the speedups of embedded microprocessor systems utilizing a high-performance coprocessor data-path., , and . J. Supercomput., 39 (3): 251-271 (2007)High-Speed FPGA Implementation of Secure Hash Algorithm for IPSec and VPN Applications., , , , and . J. Supercomput., 37 (2): 179-195 (2006)A Systematic Flow for Developing Totally Self-Checking Architectures for SHA-1 and SHA-2 Cryptographic Hash Families., , , , and . J. Circuits Syst. Comput., (2013)