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Guest Editorial., , and . J. Electron. Test., 35 (5): 579-580 (2019)Post-Silicon Gate-Level Error Localization With Effective and Combined Trace Signal Selection., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (1): 248-261 (2020)Black-Hat High-Level Synthesis: Myth or Reality?, , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (4): 913-926 (2019)Improving post-silicon error detection with topological selection of trace signals., , , , and . VLSI-SoC, page 1-6. IEEE, (2017)A Technique for Electrical Error Localization with Learning Methods During Post-silicon Debugging., , and . IGSC, page 1-8. IEEE, (2018)Unlocking Hardware Security Assurance: The Potential of LLMs., , , , , , , and . CoRR, (2023)RTL-ConTest: Concolic Testing on RTL for Detecting Security Vulnerabilities., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (3): 466-477 (2022)Circuit Topology-Aware Vaccination-Based Hardware Trojan Detection., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (9): 2852-2862 (September 2023)COPPTCHA: COPPA Tracking by Checking Hardware-Level Activity., , , and . IEEE Trans. Inf. Forensics Secur., (2020)Two Sides of the Same Coin: Boons and Banes of Machine Learning in Hardware Security., , , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 11 (2): 228-251 (2021)