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Disambiguation of "Charif, Amir"

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Fast Virtual Prototyping for Embedded Computing Systems Design and Exploration.

, , , , and . RAPIDO, page 3:1-3:8. ACM, (2019)

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Charif Haydar

Charif Mahmoudi

Manutschehr Amirfeyz

Mahmud Amirian-Khaffadjeh

Iradj Amirzadeh-Asl

 

Other publications of authors with the same name

A new approach to deadlock-free fully adaptive routing for high-performance fault-tolerant NoCs., , and . DFT, page 121-126. IEEE Computer Society, (2016)Rout3D: A lightweight adaptive routing algorithm for tolerating faulty vertical links in 3D-NoCs., , , and . ETS, page 1-6. IEEE, (2017)A Runtime Fault-Tolerant Routing Scheme for Partially Connected 3D Networks-on-Chip., , , and . DFT, page 1-6. IEEE Computer Society, (2018)A Framework for Scalable TSV Assignment and Selection in Three-Dimensional Networks-on-Chips., , , and . VLSI Design, (2017)Hybrid Prototyping Methodology for Rapid System Validation in HW/SW Co-Design., , , and . DASIP, page 35-40. IEEE, (2019)On route table computation strategies in Delay-Tolerant Satellite Networks., , , and . Ad Hoc Networks, (2018)MINI-ESPADA: A low-cost fully adaptive routing mechanism for Networks-on-Chips., , , and . LATS, page 1-4. IEEE, (2017)Detailed and highly parallelizable cycle-accurate network-on-chip simulation on GPGPU., , , and . ASP-DAC, page 672-677. IEEE, (2017)A soft-error resilient route computation unit for 3D Networks-on-Chips., , , , and . DATE, page 1357-1362. IEEE, (2018)A Dynamic Sufficient Condition of Deadlock-Freedom for High-Performance Fault-Tolerant Routing in Networks-on-Chips., , , and . IEEE Trans. Emerg. Top. Comput., 8 (3): 642-654 (2020)