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A power-effective scan architecture using scan flip-flops clustering and post-generation filling., , и . ACM Great Lakes Symposium on VLSI, стр. 517-522. ACM, (2009)A New Unicast-Based Multicast Scheme for Network-on-Chip Router and Interconnect Testing., и . ACM Trans. Design Autom. Electr. Syst., 21 (2): 24:1-24:23 (2016)Scan Flip-Flop Grouping to Compress Test Data and Compact Test Responses for Launch-on-Capture Delay Testing., , и . ACM Trans. Design Autom. Electr. Syst., 17 (2): 18:1-18:24 (2012)Fault-tolerant routing and multicasting in hypercubes using a partial path set-up., , и . Parallel Comput., 31 (3-4): 389-411 (2005)Constraining Transition Propagation for Low-Power Scan Testing Using a Two-Stage Scan Architecture., , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 54-II (5): 450-454 (2007)Low-Power Weighted Pseudo-Random Test Pattern Generation for Launch-on-Capture Delay Testing., , и . VTS, стр. 1-6. IEEE, (2020)Scan chain configuration based X-filling for low power and high quality testing., , , и . IET Comput. Digit. Tech., 4 (1): 1-13 (2010)TM: a new and simple topology for interconnection networks., , и . J. Supercomput., 66 (1): 514-538 (2013)Cooperative power scheduling for a network of MIMO links., , и . IEEE Trans. Wirel. Commun., 9 (3): 939-944 (2010)A Novel Test Application Scheme for High Transition Fault Coverage and Low Test Cost., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (6): 966-976 (2010)