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3D scaling for insulated gate bipolar transistors (IGBTs) with low Vce(sat).

K. Tsutsui, K. Kakushima, T. Hoshii, A. Nakajima, S. Nishizawa, H. Wakabayashi, I. Muneta, K. Sato, T. Matsudai, W. Saito, T. Saraya, K. Itou, M. Fukui, S. Suzuki, M. Kobayashi, T. Takakura, T. Hiramoto, A. Ogura, Y. Numasawa, I. Omura, H. Ohashi, and H. Iwai. ASICON, page 1137-1140. IEEE, (2017)

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Shinichiro Nishizawa

Shinichi Kotabe

Other publications of authors with the same name

Design Methodology for Variation Tolerant D-Flip-Flop Using Regression Analysis.S. Nishizawa, and H. Onodera. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 101-A (12): 2222-2230 (2018)Supplemental PDK for ASAP7 Using Synopsys Flow.S. Nishizawa, S. Lin, Y. Li, and H. Onodera. IPSJ Trans. Syst. LSI Des. Methodol., (2021)Libretto: An Open Cell Timing Characterizer for Open Source VLSI Design.S. Nishizawa, and T. Nakura. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 106 (3): 551-559 (March 2023)NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid Map.Y. Li, S. Lin, S. Nishizawa, H. Su, M. Fong, O. Chen, and H. Onodera. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (12): 5568-5581 (2022)A Hardware-Efficient Approximate Multiplier Combining Inexact Same-weight N:2 Compressors and Remapping Logic with Error Recovery.R. Duan, M. Zhang, Y. Guo, S. Nishizawa, and S. Kimura. SOCC, page 1-6. IEEE, (2023)Analysis and comparison of XOR cell structures for low voltage circuit design.S. Nishizawa, T. Ishihara, and H. Onodera. ISQED, page 703-708. IEEE, (2013)Variation-aware Flip-Flop energy optimization for ultra low voltage operation.T. Kamakari, S. Nishizawa, T. Ishihara, and H. Onodera. SoCC, page 17-22. IEEE, (2014)An Efficient Hardware Accelerator for Power Grid Simulation.T. Hashizume, H. Sugano, S. Nishizawa, M. Yoshikawa, and M. Fukui. ISCAS, page 2994-2997. IEEE, (2009)DC-bias-voltage dependence of degradation of aluminum electrolytic capacitors.K. Hasegawa, K. Tsuzaki, and S. Nishizawa. Microelectron. Reliab., (2018)NCTUcell: A DDA-Aware Cell Library Generator for FinFET Structure with Implicitly Adjustable Grid Map.Y. Li, S. Lin, S. Nishizawa, H. Su, M. Fong, O. Chen, and H. Onodera. DAC, page 120. ACM, (2019)

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Disambiguation of "Nishizawa, Shinichi"

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3D scaling for insulated gate bipolar transistors (IGBTs) with low Vce(sat).

Please choose a person to relate this publication to

Shinichiro Nishizawa

Shinichi Kotabe

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Nishizawa, Shinichi"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 3D scaling for insulated gate bipolar transistors (IGBTs) with low Vce(sat).

Please choose a person to relate this publication to

Shinichiro Nishizawa

Shinichi Kotabe

Other publications of authors with the same name

Disambiguation

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Chicago
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3D scaling for insulated gate bipolar transistors (IGBTs) with low Vce(sat).