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Disambiguation of "Morita, Yasuhiro"

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Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme.

, , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 90-A (12): 2695-2702 (2007)

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Takeshi Morita

Takeshi Morita

Yasuhiro Murakawa

Yasuhiro Arahata

Yasuhiro Shirasaki

 

Other publications of authors with the same name

Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme., , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 90-A (12): 2695-2702 (2007)A Feed-Forward Dynamic VDD-VBB-Frequency Management for Low Power Motion Video Compression on 90NM Risc Processor., , , , , , and . Intell. Autom. Soft Comput., 12 (3): 283-298 (2006)Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering., , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 16 (6): 620-627 (2008)Power-Minimum Frequency/Voltage Cooperative Management Method for VLSI Processor in Leakage-Dominant Technology Era., , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 88-A (12): 3290-3297 (2005)Vertical Partitioning Method for Secret Sharing Distributed Database System., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 89-A (11): 3244-3249 (2006)A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing., , , , , , and . ISVLSI, page 107-112. IEEE Computer Society, (2007)An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing., , , , , , , and . IEEE J. Solid State Circuits, 45 (10): 2057-2065 (2010)Wireless DC voltage transmission using inductive-coupling channelfor highly-parallel wafer-level testing., , , , , , , and . ISSCC, page 470-471. IEEE, (2009)Quality of a Bit (QoB): A New Concept in Dependable SRAM., , , , , , and . ISQED, page 98-102. IEEE Computer Society, (2008)A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing., , , , , , , and . IEICE Trans. Electron., 91-C (4): 543-552 (2008)