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Detecting hardware Trojans without a Golden IC through clock-tree defined circuit partitions.

, , , и . ETS, стр. 1-6. IEEE, (2017)

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Tomokazu Hattori

Tomokazu Nambu

Michiko Yoneda

 

Другие публикации лиц с тем же именем

Test pattern selection to optimize delay test quality with a limited size of test set., , , , и . European Test Symposium, стр. 260. IEEE Computer Society, (2010)Detecting hardware Trojans without a Golden IC through clock-tree defined circuit partitions., , , и . ETS, стр. 1-6. IEEE, (2017)A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips., , и . IEICE Trans. Inf. Syst., 89-D (4): 1490-1497 (2006)Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints., , , и . IEICE Trans. Inf. Syst., 91-D (3): 807-814 (2008)Area Overhead and Test Time Co-Optimization through NoC Bandwidth Sharing., , и . ATS, стр. 459-462. IEEE, (2007)Power-constrained test scheduling for multi-clock domain SoCs., , и . DATE, стр. 297-302. European Design and Automation Association, Leuven, Belgium, (2006)An integrated DFT solution for power reduction in scan test applications by low power gating scan cell., , , , и . Integr., (2017)Test Pattern Ordering and Selection for High Quality Test Set under Constraints., , , и . IEICE Trans. Inf. Syst., 95-D (12): 3001-3009 (2012)Power-Aware Multi-Frequency Heterogeneous SoC Test Framework Design with Floor-Ceiling Packing., , , и . ISCAS, стр. 2942-2945. IEEE, (2007)A DFT Method for Time Expansion Model at Register Transfer Level., , и . DAC, стр. 682-687. IEEE, (2007)