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A Unified Amplifier-Based CC-CV Linear Charger for Energy-Constrained Low-Power Applications.

, , and . IEEE Trans. Circuits Syst. II Express Briefs, 66-II (2): 377-381 (2019)

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An energy-efficient SAR ADC using a single-phase clocked dynamic comparator with energy and speed enhanced technique., and . IEICE Electron. Express, 14 (8): 20170219 (2017)A Unified Amplifier-Based CC-CV Linear Charger for Energy-Constrained Low-Power Applications., , and . IEEE Trans. Circuits Syst. II Express Briefs, 66-II (2): 377-381 (2019)An 8-Bit 10-GS/s 16× Interpolation-Based Time-Domain ADC With <1.5-ps Uncalibrated Quantization Steps., , , and . IEEE J. Solid State Circuits, 55 (12): 3225-3235 (2020)A 13.56-MHz CMOS Active Rectifier With a Voltage Mode Switched-Offset Comparator for Implantable Medical Devices., , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (10): 2050-2060 (2018)High-speed low-power decimation filter for wideband Delta-Sigma ADC., , , and . MWSCAS, page 591-594. IEEE, (2014)A 20GS/s 8b Time-Interleaved Time-Domain ADC with Input-Independent Background Timing Skew Calibration., , , and . VLSI Circuits, page 1-2. IEEE, (2021)22.1 A 12GS/s 12b 4× Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer., , , , and . ISSCC, page 388-390. IEEE, (2024)A 52.5-dB 2× Time-Interleaved 2.8-GS/s SAR ADC With 5-bit/Cycle Time-Domain Quantization and a Compact Signal DAC., , , , and . IEEE J. Solid State Circuits, 58 (12): 3586-3597 (December 2023)Background Calibration of Bit Weights in Pipelined-SAR ADCs Using Paired Comparators., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (4): 1074-1078 (2020)Forecasting the Trend of COVID-19 Considering the Impacts of Public Health Interventions: An Application of FGM and Buffer Level., , , and . J. Heal. Informatics Res., 5 (4): 497-528 (2021)